Micron Document




IBM Telum
──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────
top
Telum is a microprocessor made by IBM for the IBM z16 series mainframe computers.cite-ref-2021-08-23-forbes-2-0[2]cite-ref-2022-04-29-ieee-spectrum-3-0[3] The processor was announced at the Hot Chips 2021 conference on 23 August 2021.cite-ref-2021-08-23-forbes-2-1[2] Telum is IBM's first processor that contains on-chip acceleration for artificial intelligence inferencing while a transaction is taking place.cite-ref-2021-08-24-techrepublic-4-0[4]cite-ref-2021-08-26-sce-5-0[5]

Contents


──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────

Description

The chip contains 8 processor cores with a deep superscalar out-of-order pipeline, running with more than 5 GHz clock frequency which is optimized for the demands of heterogenous enterprise-class workloads (e.g: finance, security sensitive applications, applications requiring extreme reliability). The cache and chip-interconnection infrastructure provides 32 MB cache per core and can scale to 32 Telum chips.cite-ref-2021-09-02-anandtech-6-0[6]cite-ref-2022-04-29-ieee-spectrum-3-1[3]cite-ref-2022-04-05-yt-ltt-7-0[7] The cache design has been described as "revolutionary" in 2021, cite-ref-2021-09-02-anandtech-6-1[6] by creating a system where the L2 cache of one core can be used as virtual L3 and L4 caches for another core.cite-ref-2022-04-29-ieee-spectrum-3-2[3]cite-ref-2023-07-24-ars-1-1[1] The Telum processor can either be water cooled or air cooled, but water cooling is required for running more than a few Telum processors in a single IBM compute drawer.cite-ref-0-8-0[8]cite-ref-1-9-0[9] Unlike other processors, the IBM Telum does not thermal throttle by reducing clock speed; instead it inserts sleep state instructions.cite-ref-0-8-1[8]cite-ref-1-9-1[9]

Telum adds a new, NNP-Data-Type-1 Format, 16-bit floating point format and several new instructions. The Neural Network Processing Assists (NNPA)cite-ref-10[10] instruction performs a variety of tensor instructions useful for neural networks.

See also
References

cite-note-2023-07-24-ars-11. citerefhudson2023Hudson, Andrew (24 July 2023). "The IBM mainframe: How it runs and why it survives". Ars Technica. Retrieved 25 July 2023.
cite-note-2021-08-23-forbes-22. citerefmoorhead2021Moorhead, Patrick (23 August 2021). "IBM Telum- A New Chapter In Vertically Integrated Chip Technology". Forbes. Retrieved 12 May 2023.
cite-note-2022-04-29-ieee-spectrum-33. citerefjohnson2022Johnson, Dexter (29 April 2022). "IBM's New Telum Chip Reboots the Mainframe". IEEE Spectrum. Retrieved 5 May 2022.
cite-note-2021-08-24-techrepublic-44. citerefcombs2021Combs, Veronica (24 August 2021). "IBM's new Telum Processor is the company's first with an on-chip AI accelerator". TechRepublic. Archived from the original on 2023-03-22. Retrieved 27 August 2021.
cite-note-2021-08-26-sce-55. citerefsperling2021Sperling, Ed (26 August 2021). "New Approaches For Processor Architectures". Semiconductor Engineering. Retrieved 25 July 2023.
cite-note-2021-09-02-anandtech-66. citerefcutress2021Cutress, Ian (2 September 2021). "Did IBM Just Preview The Future of Caches?". Anandtech. Archived from the original on September 2, 2021. Retrieved 5 May 2022.
cite-note-2022-04-05-yt-ltt-77. citerefsebastian2022Sebastian, Linus (5 April 2022). "I Tried to Break a Million Dollar Computer - IBM Z16 Facility Tour!" (video). YouTube. Linus Media Group. Retrieved 5 May 2022.
cite-note-0-88. IBM z16 Technical Introduction (PDF) (Second ed.). IBM. April 2023. SG24-8950-01.
cite-note-1-99. Why Do Mainframes Still Exist? What's Inside One? 40TB, 200+ Cores, AI, and more!, 28 October 2023, retrieved 2024-01-11
cite-note-1010. citerefz"NEURAL NETWORK PROCESSING ASSIST" (PDF). z/Architecture Principles of Operation (PDF) (Fourteenth ed.). IBM. May 2022. pp. 26-61 – 26-96. SA22-7832-13. Retrieved March 31, 2025.